1. Introduction
1.1 A Historical Perspective
1.2 Issues in Digital Integrated Circuit Design
1.3 Quality Metrics of a Digital Design
2. The Manufacturing Process
2.1 Manufacturing CMOS Integrated Circuits
2.2 Design Rules
2.3 Packaging Integrated Circuits
3. The Devices
3.1 Diode
3.2 MOS Transistor
3.3 Process Variations
3.4 Technology Scaling
4. The Wire
4.1 Interconnect Parameters-Capacitance, Resistance, and Inductance
4.2 SPICE Wire Models
5. The CMOS Inverter
5.1 Static CMOS Inverter
5.2 Evaluating the Robustness of the CMOS Inverter
5.3 Performance of CMOS Inverter
5.4 Power, Energy Delay
5.5 Technology Scaling and Its Impact
6. Designing Combinational Logic Gates in CMOS
6.1 Static CMOS Design
6.2 Dynamic CMOS Design
6.3 CMOS Design Summary
7. Designing Sequential Logic Circuits
7.1 Static Latches and Registers
7.2 Dynamic Latches and Registers
7.3Aternative Registers
7.5 Pipelining Optimization
7.6 Nonbistable Sequential Circuits
7.7 Choosing a Clocking Strategy
8. Coping with Interconnect
8.1 Capacitive Parasitics
8.2 Resistive Parasitics
8.3 Inductive Parastics
8.4 Advanced Interconnect Techniques
9. Timing Issues in Digital Circuits
9.1Timing Classification of Digital Systems
9.2 Synchronous Design
9.3 Self-Timed Circuit Design
9.4 Synchronizers and Arbiters
9.5 Clock Synthesis and Synchronization Using a Phase-Locked Loop
10. Designing Arithmetic Building Blocks
10.1 Datapaths in Digital Processor Architectures
10.2 Adder
10.3 Multiplier
10.4 Shifter
10.5 Other Arithmetic Operators 10.6 Design as a Trade-off